FIG. 1 is a schematic diagram illustrating a memory cell of a dual-port SRAM. The memory cell 100 includes a latching circuit 110, and four pass gates APG1, APG2, BPG1, BPG2.
In the latching circuit 110, the output terminal of an inverter 104 is connected to the input terminal of an inverter 102, and the input terminal of the inverter 104 is connected to the output terminal of the inverter 102. Furthermore, the output terminal of the inverter 104 is used as the output terminal O of the latching circuit 110, and the output terminal of the inverter 102 is used as the inverse output terminal OB of the latching circuit 110.
Furthermore, each memory cell 100 has two ports (hereinafter, port A and port B). In the port A, the ON and OFF statuses of both the first pass gate AGP1, and the second pass gate APG2 of the port A are controlled by the word line AWL of the port A. Accordingly, the write data can be stored in the memory cell through the bit line ABL, and the inverse bit line ABLB of the port A. Alternatively, the data stored in the memory cell 100 can be read through the bit line ABL, and the inverse bit line ABLB of the port A.
Similarly, the ON and OFF statuses of both the first pass gate BGP1 and the second pass gate BPG2 of the port B are controlled by the word line BWL of the port B. Accordingly, the write data can be stored in the memory cell through the bit line BBL, and the inverse bit line BBLB of the port B. Alternatively, the data stored in the memory cell 100 can be read through the bit line BBL, and the inverse bit line BBLB of the port B.
Furthermore, the first pass gate APG1 of the port A is connected between the bit line ABL of the port A, and the output terminal O of the latching circuit 110. In addition, the control terminal of the first pass gate APG1 of the port A is connected to the word line AWL of the port A. The second pass gate APG2 of the port A is connected between the inverse bit line ABLB of the port A, and the inverse output terminal OB of the latching circuit 110. In addition, the control terminal of the second pass gate APG2 of the port A is connected to the word line AWL of the port A.
The first pass gate BPG1 of the port B is connected between the bit line BBL of the port B, and the output terminal O of the latching circuit 110, and the control terminal of the first pass gate BPG1 of the port B is connected to the word line BWL of the port B. The second pass gate BPG2 of the port B is connected between the inverse bit line BBLB of the port B, and the inverse output terminal OB of the latching circuit 110, and the control terminal of the second pass gate BPG2 of the port B is connected to the word line BWL of the port B.
Basically, the word line AWL, the bit line ABL, and the inverse bit line ABLB of the port A may be considered as port A signals of the memory cell 100. The word line BWL, the bit line BBL, and the inverse bit line BBLB of the port B may be considered as port B signals of the memory cell 100. In addition, a control circuit (not shown) connected to the memory cell 100 may proceed a read operation or a write operation to the memory cell 100 through the port A signals or the port B signals of the memory cell 100. Related operations of the memory cell of the dual-port SRAM are briefly illustrated below.
FIGS. 2A and 2B are schematic diagrams illustrating the port A signals are utilized in the read operation to the memory cell. The output terminal O of the latching circuit 110 is with a high level voltage (Vcc), and the inverse output terminal OB of the latching circuit OB is with a low level voltage (0V).
As shown in FIG. 2A, the control circuit (not shown) pre-charges the bit line ABL, and the inverse bit line ABLB of the port A to the high level voltage (Vcc) before the word line AWL of the port A operates. That is, the word line AWL of the port A is 0V. Then, the bit line ABL and the inverse bit line ABLB of the port A are left floating.
As shown in 2B, when the word line AWL of the port A operates (voltage of the word line AWL of the port A is Vcc), the first pass gate (APG1), and the second pass gate (APG2) of the port A are turned on. Since the output terminal O of the latching circuit 110 is at the high level voltage (Vcc), the bit line ABL of the port A remains at the high level voltage (Vcc). Furthermore, since the inverse output terminal OB is at the low level voltage (0V), a discharge current Id flowing from the inverse bit ABLB line of the port A to the inverse output OB of the latching circuit 110 is generated. Thus, the inverse bit line ABLB of the port A changes to the low level voltage (0V). Therefore, the data stored in the memory cell 100 can be retrieved through the voltages of the bit line ABL, and the inverse bit line ABLB of the port A. Then, the read operation is complete.
Similar to the operations shown in FIGS. 2A and 2B, the memory cell can be read through the port B signals.
Furthermore, the memory cell 100 of dual-port SRAM mentioned above features that both the port A signals and the port B signals can be simultaneously utilized in the read operation. In other words, the control circuit (not shown) can freely utilize either port A signals, port B signals, or both port A signals and port B signals to proceed the read operation.
FIGS. 3A and 3B are schematic diagrams illustrating the write operation of the memory cell through the port A signals. The output terminal O of the latching circuit is high level (Vcc) and the inverse output terminal OB of the latching circuit 110 is low level (0V). Furthermore, the control circuit (not shown) will store the low level (0V) in the memory cell 100.
As shown in FIG. 3A, the word line AWL of the port A is 0V before operates, and the control circuit (not shown) provides the low level (0V) to the bit line ABL of the port A, and the high level (Vcc) to the inverse bit line ABLB of the port A.
As shown in 3B, when the word line AWL of the port A operates (voltage of the word line AWL of the port A is Vcc), the first pass gate (APG1) and the second pass gate (APG2) of the port A are turned on. Since the bit line ABL of the port A is 0V, a discharge current Id flowing from the output terminal O of the latching circuit 110 to the bit line ABL of the port A is generated. Consequentially, the output terminal O of the latching circuit 110 changes to the low level voltage (0V). Meanwhile, as the inverse bit line ABLB of the port A is at the high level voltage (Vcc), a charging current Ic flowing from the inverse bit ABLB line of the port A to the inverse output OB of the latching circuit 110 is generated. Thus, the inverse output OB will change to the high level voltage (Vcc), and the write operation is complete.
Similar to the operations illustrated in FIGS. 3A and 3B, the port B signals of the memory cell can be utilized for write operation.
Another feature of the above memory cell 100 of the dual-port SRAM is to utilize port signals of a single port to execute the read operation to the memory cell 100, and utilize port signals of another port to execute the write operation. However, while executing the above read operation, and the write operation, write disturbance may occur and result in write failure. In consequence, data cannot be correctly written to the memory cell 100. Details are illustrated below.
FIGS. 4A to 4C are schematic diagrams illustrating port A signals are utilized to execute the write operation to the memory cell, and the port B signals are utilized to execute the read operation to the memory cell. The voltage of the output terminal O of the latching circuit 110 is high level (Vcc), and the voltage of the inverse output terminal OB of the latching circuit 110 is low level (0V). Furthermore, the control circuit (not shown) will store the low level (0V) to the memory cell 100.
As shown in FIG. 4A, before the word line AWL of the port A, and the word line BWL of the port B operate, the control circuit (not shown) provides the low level (0 V) to the bit line ABL of the port A, and the high level (Vcc) to the inverse bit line ABLB of the port A. In addition, the control circuit (not shown) pre-charges both the bit line BBL and the inverse bit line of the port B to the high level voltage (Vcc) before left them floating.
As shown in FIG. 4B, when both the word line AWL of the port A, and the word line BWL of the port B operate, the first and the second pass gates APG1, APG2 of the port A, and the first and the second pass gates BPG1, BPG2 of the port B are all turned on. Since the bit line BBL of the port B is high level (Vcc), and the bit line ABL of the port A is low level (0V), a discharge current Id is generated from the bit line BBL of the port B. The discharge current Id flowing from the output terminal O of the latching circuit 110 to the bit line ABL of the port A is generated, and the write disturbance is accordingly caused.
Furthermore, the phenomenon that the voltage of the output terminal O of the latching circuit 110 cannot change to the low level (0V) due to the write disturbance is defined as the write failure.
As shown in FIG. 4C, the word line AWL of the port A, and the word line BWL of the port B operate between time point t1, and time point t2. Between the time point t1 and the time point t2, write disturbance (duration I) is generated because the discharge current Id flows from the bit line BBL of the port B to the bit line ABL of the port A, through the output terminal O of the latching circuit 110. Thus, at the time point t2, the output terminal O of the latching circuit 110 cannot change to the low level (0V) but maintains as the high level (Vcc). In consequence, the write failure occurs (duration II).
According to the above illustrations, the port A, and the port B are respectively utilized for the write operation, and the read operation. In a case that the voltage of the bit line ABL of the port A, and the bit line BBL of the port B port are different, and both the word line AWL of the port A, and the word line BWL of the port B operate at the same time, a discharge current between the two bit lines ABL, BBL will be generated, and the write disturbance occurs.
Similarly, if the voltages of the inverse bit line ABLB of the port A, and the inverse bit line BBLB of the port B are different, and both the word line AWL of the port A and the word line BWL of the port B operate at the same time, a discharge current between the two inverse bit lines ABLB, BBLB will be generated, and the write disturbance occurs.
FIG. 5 is a schematic diagram illustrating a curve of write disturbance of a conventional dual-port SRAM. In FIG. 5, Tsk represents a timing skew between the two word lines AWL, BWL, and Vcc represents a high level voltage. Basically, the timing skew between two word lines AWL, BWL is a factor of affecting the write disturbance, and Vcc is another factor.
For example, when the port A signals are utilized for the write operation, and the port B signals are utilized for the read operation, the timing difference between operation of the word line AWL of the port A, and operation of the word line BWL of the port B is defined as Tsk. That is, when the word line AWL of the port A, and the word line BWL of the port B operate simultaneously, Tsk is equal to 0. When operation of the word line AWL of the port A is prior to operation of the word line BWL of the port B, Tsk is greater than 0. When the word line AWL of the port A operates later than the word line BWL of the port B, Tsk is less than 0.
As shown in FIG. 5, when the word line AWL of the port A, and the word line BWL of the B port operate at the same time (Tsk=0), the high level voltage (Vcc) must be at least greater than 700 mV. Otherwise, the write disturbance will cause the wire failure.
When operation of the word line BWL of the port B prior to operation of the word line AWL of the port A, and the Tsk is greater than 0.10 ns s(Tsk<−0.10 ns), the high level voltage (Vcc) is 600 mV, and the write disturbance barely occurs. Moreover, when operation of the word line BWL of the port B is prior to operation of the word line AWL of the port A, and the Tsk is less than 0.10 ns s(−0.10 ns<Tsk<0), the high level voltage (Vcc) must be greater than 600 mV. Otherwise, the write disturbance will result in the write failure.
When operation of the word line AWL of the port A is prior to operation of the word line BWL of the port B, and the Tsk is greater than 1 ns(Tsk>1 ns), the high level voltage (Vcc) is 600 mV and the write disturbance barely occurs. Moreover, when operation of the word line AWL of the port A is prior to operation of the word line BWL of the port B, and the Tsk is less than 1 ns (0<Tsk<1 ns), the high level voltage (Vcc) must be greater than 600 mV. Otherwise, the write disturbance will result in the write failure. Especially when Tsk is 0.25 ns, the write disturbance affects severely, and the high level voltage (Vcc) must be greater than 900 mV to prevent the write failure.